1. Technical Field
The present disclosure relates to digital signal transmission, in particular, to a determining sampling frequency method and a device thereof for a single wire transmission interface.
2. Description of Related Art
The single wire transmission interface can be used to transmit digital signal. For example, Sony/Philips Digital Interface Format (S/PDIF) which is included in the IEC 60958 standard is a single wire transmission interface. The signals in such single wire transmission interface include data and clock message. Due to single wire design, it means that the data providing terminal (e.g., output terminal of the S/PDIF) also controls the clock frequency. In order to receive all messages correctly, in general, the receiving terminal (e.g. receiving terminal of the S/PDIF) will utilize the clock with higher frequency to acquire data or utilize the analog module with clock and data recovery circuit to recover the clock and the data so as to receive data correctly.
Referring to FIG. 1, FIG. 1 is a circuit block diagram illustrating a conventional clock and data recovery circuit. When the data of the input signal IN are acquired by analog means, the clock and data recovery circuit 10 can be utilized to recover the clock signal CLK″ (recovered clock signal) and the data signal DATA″ (recovered data signal). The digital circuit section only needs to acquire the recovered data signal according to the recovered clock signal so as to receive the data correctly. However, in order to acquire the data supporting wide range sampling frequency, it would be another challenge for the analog circuit. In order to lock the sampling frequency correctly, it may need more cost on algorithm design and operating time for the algorithm.